An 8T SRAM Array with Configurable Word Lines for In …
Jan 27, 2021 · In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes.
A 65-nm 8T SRAM Compute-in-Memory Macro With Column …
Apr 11, 2022 · A test chip with a 16K 8T SRAM bitcell array is fabricated using a 65-nm process. The measured energy efficiency is 490–15.8 TOPS/W for 1–5 bit ADC resolution using 0.45-/0.8-V core supply.
Configurable 8T SRAM for Enbling in-Memory Computing
The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and …
A Reliable 8T SRAM for High-Speed Searching and Logic-in …
We have validated the proposed 8T CSRAM design in a 16 Kb array with a 28-nm CMOS technology. Compared to the state-of-the-art 8 T CSRAM, results show that our design is not only reliable but also 3.1 times faster, with a maximum operating frequency upping to 2.44 GHz.
In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes.
8T-SRAM cell with Improved Read and Write Margins in 65 ...
Nov 25, 2015 · SRAM operation at subthreshold/weak inversion region provides a significant power reduction for digital circuits. SRAM arrays which contribute to a large amount of power consumption for the processors in sub-100 nm technologies, however, cannot benefit from subthreshold operation.
Single bit‐line 8T SRAM cell with asynchronous dual word‐line …
Oct 29, 2018 · The SRAM array was implemented with 64 rows and 64 columns and a distance-4 bit-interleaving architecture. The array is further divided into four local blocks. Each local block comprises of a local array of 16 rows × 64 columns, pre-charge circuitry, and sensing logics.
A 4 × 4 8T-SRAM array with single-ended read and differential …
May 7, 2021 · The proposed SRAM array is designed with an optimized 8T SRAM cell with minimum leakage and improved stability. The cell designed with 22 nm CMOS technology uses a stacking effect to further enhance leakage reduction and transmission gate as an access transistor to obtain better stability.
[PDF] An 8T SRAM Array with Configurable Word Lines for In …
Jan 27, 2021 · In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes.
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic …
This study proposes a bidirectional static random access memory (SRAM) array structure comprising self-cycling eight-transistor (8T) cells, which can achieve full-array Boolean logic operations and read/write in two directions.